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data sheet 1 rev. 1.0, 2014-02-03 7 a h-bridge for dc-motor applications TLE7209-3R 1overview 1.1 features ? operating supply voltage 5 v to 28 v ? typical r dson = 150 m for each output transistor (at 25 c) ? continuous dc load current 5 a ( t c < 100 c) ? output current limitation at typ. 6.6 a 1.1 a ? short circuit shut-down for output currents over 8 a ? logic- inputs ttl/cmos-compatible ? output switching frequency up to 30 khz ? rise and fall times optimized for 0.5-2 khz ? over-temperature protection ? short circuit protection ? undervoltage disable function ? diagnostic by spi or status-flag (configurable) ? enable and disable inputs ? pg-dso-20-65 power package ? green product (rohs compliant) functional description the TLE7209-3R is an intelligent full h-bridge, designed for the control of dc and stepper motors in safety critical appl ications and under extreme environmental conditions. the h-bridge is protected against over-temper ature and short circuits and has an under voltage lockout for all the supply voltages ? v s ? (main dc power supply). all malfunctions cause the output stages to go tristate. the device is configurable by the dms pin. when grounded, the device gives diagnostic information via a simple error flag. when supplied with v cc = 5 v, the device works in spi mode. in this mode, detailed failure diagnosis is available via the serial interface. type package TLE7209-3R pg-dso-20-65
tle 7209-3r overview data sheet 2 rev. 1.0, 2014-02-03 1.2 pin configuration figure 1 pinout TLE7209-3R table 1 pin definitions and functions pin. no. symbol function 1 gnd ground 2 sck/sf spi-clock/status-flag 3in1input 1 4 nc not connected 5, 16 v s supply voltage; connect pins externally 6, 7 out1 output 1; connect pins externally 8 sdo serial data out 9 sdi serial data in 10 gnd ground 11 gnd ground 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 dms en out2 gnd dis sdi sdo out1 out1 nc in1 gnd gnd gnd out2 sck/sf v s v s csn in2 metal slug is connected to gnd pins internally
tle 7209-3r overview data sheet 3 rev. 1.0, 2014-02-03 12 dms diagnostic-mode selection (+ supply voltage for spi-interface) 13 en enable 14, 15 out2 output 2; connect pins externally 17 csn chip select (low active) 18 dis disable 19 in2 input 2 20 gnd ground table 1 pin definitions and functions (cont?d) pin. no. symbol function
tle 7209-3r overview data sheet 4 rev. 1.0, 2014-02-03 1.3 block diagram figure 2 block diagram TLE7209-3R bias charge pump under voltage fault- detect dms en sdo sck/sf sdi csn in1 in2 v s gnd out 2 out 1 dis driver & gate- control direct input 8 bit logic and latch spi over temperature
tle 7209-3r circuit description data sheet 5 rev. 1.0, 2014-02-03 2 circuit description 2.1 control inputs the bridge is controlled by the input s in1, in2, dis and en as shown in table 2 . the outputs out1 and out2 are set to high or low by the parallel inputs in1 and in2, respectively. in addition, the outputs can be di sabled (set to tristate) by the disable and enable inputs dis and en. inputs in1, in2 and dis have an internal pu ll-up. input en has an internal pull-down. table 2 functional truth table pos. dis en in1 in2 out1 out2 sf 1) 1) if mode ?status-flag? is selected (see chapter 2.4 ) spi 2) dia_reg 2) if mode ?spi-diagnosis? is selected (see chapter 2.4 ) 1. forward l h h l h l h see chapter 2.4.2 2. reverse l hl hl h h 3. free-wheeling low l h l l l l h 4. free-wheeling high l hhhh h h 5. disable hxxxz z l 6. enable x l x x z z l 7. in1 disconnected l h z x h x h 8. in2 disconnected l h x z x h h 9. dis disconnected z xxxz z l 10. en disconnected x z x x z z l 11. current limit. active l h x x z z h 12. under voltage xxxxz z l 13. over-temperature xxxxz z l 14. over-current xxxxz z l
tle 7209-3r circuit description data sheet 6 rev. 1.0, 2014-02-03 2.2 power stages four n-channel power-dmos transistors build up the output h-bridge. integrated circuits protect the outputs against over current and ov er-temperature if there is a short-circuit to ground, to the supply voltage or across the load. positive and negative voltage spikes, which occur when switching inductive loads, are limited by integrated freewheeling diodes. to drive the gates of the high-side dmos, an internal charge pump is integrated to generate a voltage higher than the supply voltage. 2.2.1 chopper current limitation to limit the output curr ent at low power loss, a chopper current limitation is integrated as shown in figure 3 . the current is measured by sens e cells integrated in the low-side switches. when the current limit i l has been exceeded for a time t b , all output stages are switched off for a fixed time t a . figure 3 chopper current limitation i out current limit i l switch-off time t a time blanking time t b
tle 7209-3r circuit description data sheet 7 rev. 1.0, 2014-02-03 2.2.2 temperature-depending current reduction for t ilr < t j TLE7209-3R is protected against short circuits, overload and invalid supply voltage by the following measures: 2.3.1 short circuit to ground the high-side switches are protected against a short of the output to ground by an over current shut-down. if a high-side switch is tu rned on and the current rises above the short circuit detection current i ouk all output transistors are turned off after a typical filter time of 2 s, and the error bit ?short circuit to groun d on output 1 (2)?, scg1 (scg2) is stored in the internal status register. 2.3.2 short circuit to v s due to the chopper current regulation, the low-side switches are already protected against a short to the supply voltage. to be able to distinguish a short circuit from normal current limit operation, the current limitat ion is deactivated for the blanking time t b after the current has exceeded the current limit threshold i l . if the short circuit detection current i ouk is reached within this blanking time, a short circuit is detected (see figure 5 ). all output transistors are turned off an d the according error bit ?short circuit to battery on output 1 (2)?, scb1 (scb2) is set. a 6.6a 2.5a tj c t sd tol er ance of temper atur e dependent cur r ent r educti on r ange of over - temper atur e shut- down i l t ilr
tle 7209-3r circuit description data sheet 8 rev. 1.0, 2014-02-03 figure 5 short to vs detect ion. left: normal op eration. right: short circuit is detected 2.3.3 short circuit across the load if short circuit messages from high- and lo w-side switch occur simultaneously within a delay time of typically 2 s, the error bit ?short circu it over load?, scol is set. 2.3.4 over-temperature in case of high dc-currents, insufficient cooling or high ambient temperature, the chip temperature may rise above the thermal shut-down temperature t sd . in that case, all output transistors are shut-down and the error-bit ?over-temperature?, ot is set. 2.3.5 under-voltage shut-down if the supply-voltage at the v s pins falls below the under-voltage detection threshold, the outputs are set to tristate and the error-bit ?under-voltage at v s ? is set. 2.4 diagnosis the diagnosis-mode can be selected be tween spi-diagnosis and status-flag diagnosis. the choice of the diagnosis-mode is selected by the voltage-level on pin 12 (dms diagnosis mode selection): ? dms = gnd, status-flag mode ?dms = v cc , spi-diagnosis mode for the connection of pins sdi, sdo, csn and sck/sf see figure 14 and figure 15 . i out i l time t b i ouk in i out i l time t b i ouk in t a t b
tle 7209-3r circuit description data sheet 9 rev. 1.0, 2014-02-03 2.4.1 status-flag (sf) mode (dms = gnd) 2.4.1.1 sf output in sf-mode, pin 2 is used as an open-drain output status-flag. the pin has to be pulled to the logic supply voltage with a pull-up resistor, 47 kohm recommended. in case of any failure that leads to a shut-dow n of the outputs, the st atus-flag is set (e.g. sf pin pulled to low). these failures are: ? under voltage on v s ? short circuit of out1 or out2 against v s or gnd ? short circuit between out1 and out2 ? over-current ? over-temperature sf is also pulled low when the outputs are disabled by en or dis. 2.4.1.2 fault storage and reset ? in case of under-voltage , the failure is not latched. as soon as v s falls below the under-voltage detection threshold, the output stage switches in tristate and the status- flag is set from high level to low-level. if the voltage has risen above the specified value again, the output stage switc hes on again and the status-flag is reset to high-level. the under voltage failure is shown at the sf pin for v s in the voltage range below the detection threshold (typical 4.2v) down to 2.5v. ? in the sf-mode, all internal circuitry is supplied by the voltage on v s . for that reason, a loss of v s supply voltage leads to a reset of all stored information ( power-on- reset ). this power-on-reset occurs as soon as under-voltage is detected on v s ? in case of short circuit, over-current or over-temperature , the fault will be stored. the output stage remains in tristate and t he status-flag at low-level until the error is reset by one of the following conditions: h -> l on dis, l -> h on en or power-on reset. 2.4.2 spi-mode (dms = 5v) 2.4.2.1 spi-interface the serial spi interface establishes a comm unication link between TLE7209-3R and the systems microcontroller. the TLE7209-3R a lways operates in slave mode whereas the controller provides the master function. th e maximum baud rate is 2 mbaud (200pf on sdo). by applying an active slave se lect signal at csn the TLE7209-3R is selected by the spi master. sdi is the data input (slave in), sdo the data output (slave out). via sck (serial clock input) the spi clock is provided by the master. in case of inactive slave select signal (high) the data output sdo goes into tristate.
tle 7209-3r circuit description data sheet 10 rev. 1.0, 2014-02-03 the first two bits of an instruction may be used to establish an extended device- addressing. this gives the opportunity to operate up to 4 slave-devices sharing one common csn signal from the master-unit (see figure 7 ) figure 6 spi block-diagram 2.4.2.2 characteristics of the spi interface 1. when dms is > 3.5v, the spi is active, ind ependently of the state of en or dis. during active reset conditions (dms < 3.5v) the spi is driven into its default state. when reset becomes inactive, the state machine enters in to a wait-state for the next instruction. 2. if the slave select signal at csn is inacti ve (high), the state machine is forced to enter the wait-state, i.e. the state machine waits for th e following instruction. 3. during active (low) state of the select si gnal csn the falling edge of the serial clock signal sck will be used to latch the input data at sdi. output data at sdo are driven with the rising edge of sck (see timing diagram figure 13 ) 4. chip-address: in order to establish the option of extended addressing the uppermost two bits of the instruction-byte (i.e the first two sdi-bits of a frame) are reserved to send a chip- address. to avoid a bus conf lict the output sdo must stay high impedance during the addressing phase of a frame (i.e. until the a ddress-bits are recognized as valid chip- address). if the chip-address does not match, the data at sdi will be ignored and sdo remains high impedance for the complete frame. see also figure 7 5. verification byte: simultaneously to the receipt of an spi instruction TLE7209-3R transmits a verification byte via the output sdo to the controller. refer to figure 8 . this byte indicates normal or abnormal operation of the spi . it contains an initial bit pattern and a flag indicating an error occurred during the previous access. csn dms sck sdi sdo shift-register spi-control: -> state m achine -> clock counter -> in s tru c tio n re c o g n itio n spi power- supply dia_reg diagnostics 8 8 or en dis reset dms under- voltage
tle 7209-3r circuit description data sheet 11 rev. 1.0, 2014-02-03 6. because only read access is used in the TLE7209-3R, the sdi data-bits (2nd byte) are not used 7. invalid inst ruction/access: an instruction is invalid if an unused inst ruction code is detect ed (see tables with spi instructions). in case an unused instru ction code occurred, the data byte ?ff hex ? (no error) will be transmitted after having sent the verification byte. this transmission takes place within the same spi-frame that contained the unused instruction byte. in addition any transmission is invalid if the number of spi clock pulses (falling edge) counted during active csn differs from exactly 16 clock pulses. if an invalid instruction is detected, bit trans_f in the following verification byte (next spi transmission) is set to high. the trans_f bit must not be cleared before it has been sent to the microcontroller. 8. transfer error bit trans_f: the bit trans_f indicates an error during the previous transfer. an error is considered to have occurred when an invalid command was sent, the number of spi clock pulses (falling edge) counted during active csn was less than or greater than 16 clock pulses, or spi clock (sck) was logical high during falling edge of csn.
tle 7209-3r circuit description data sheet 12 rev. 1.0, 2014-02-03 figure 7 bus-arbitration by chip-address z 0 7 654 3 210 7 6 5 43 2 1 7 1 2 3 4 5 6 7 0 1 2 3 4 5 6 0 sdi sck csn 1 2 3 4 5 6 7 0 1 2 3 4 5 sdo 0 address sent by master is "00" sdo remains tristated after csn active correct addres is recognized, data transmitted to sdo z 0 7 654 3 210 7 6 5 43 2 1 7 1 2 3 4 5 6 7 0 1 2 3 4 5 6 0 sdi sck csn sdo address sent by master is differnt from "00" sdo remains tristated after csn active correct addres is not recognized, sdo remains tristated and sdi data are ignored
tle 7209-3r circuit description data sheet 13 rev. 1.0, 2014-02-03 2.4.2.3 spi-communication the 16 input bits consist of the spi-instruc tion byte and a second, unused byte. the 16 output bits consist of the verificati on-byte and the data-byte (see also figure 8 ). the definition of these bytes is gi ven in the subsequent sections. figure 8 spi communication 2.4.2.4 spi instruction the uppermost 2 bit of the instruction byte contain the chip-address. the chip-address of the TLE7209-3R is 00. during read-access, the output data according to the register requested in the instruction byte are appli ed to sdo within the same spi frame. that means, the output data corresponding to an instruction byte sent during one spi frame are transmitted to sdo during the same spi frame. table 3 spi instruction format msb 76543210 0 0 instr4 instr3 instr2 instr1 instr0 insw table 4 spi instruction description bit name description 7,6 cpad1,0 chip address (has to be ?0?, ?0?) 5-1 instr (4-0) spi instruction (encoding) 0 insw even parity 0 7 654 3 210 7 6 5 43 2 1 sdi sck csn sdo spi instruction not used msb lsb verification byte data-byte msb lsb msb lsb
tle 7209-3r circuit description data sheet 14 rev. 1.0, 2014-02-03 2.4.2.5 verification byte the default value after power-up at dms of t he trans_f bit is l (previous transfer valid) table 5 spi instruction-bytes encoding spi instruction encoding description bit 7,6 cpad1,0 bit 5-1 instr(4-0) bit 0 insw rd_ident 00 00000 0 read identifier rd_version 00 00001 1 read version rd_dia 00 00100 1 read dia_reg ? 00 all others x unused, trans_f is set to high, ff_hex is sent as data bit ? all others xxxxx x invalid address, sdo remains tristate during entire spi frame table 6 verification byte format msb 76543210 zz10101trans_f table 7 verification byte description bit name description 0 trans_f bit = 1: error detected during previous transfer bit = 0: previous transfer was recognized as valid 1 fixed to high 2 fixed to low 3 fixed to high 4 fixed to low 5 fixed to high 6 send as high impedance 7 send as high impedance
tle 7209-3r circuit description data sheet 15 rev. 1.0, 2014-02-03 2.4.2.6 data-byte: diagnosti cs/encoding of failures (register dia_reg, spi instruction rd_dia) ) table 8 dia_reg format msb 76543210 en/dis ot currred currlim dia21 dia20 dia11 dia10 table 9 dia_reg description default value after reset is ff hex . access by controller is read only bit name description latch behavior 0 dia 10 diagnosis-bit1 of out1 see below 1 dia 11 diagnosis-bit2 of out1 see below 2 dia 20 diagnosis-bit1 of out2 see below 3 dia 21 diagnosis-bit2 of out2 see below 4 currlim is set to ?0? in case of current limitation. latched 5 currred is set to ?0? in case of temperature dependent current limitation latched 6 ot is set to ?0? in case of over-temperature latched 7 en/dis is set to ?0? in case of en = l or dis = h not latched en dis dia_reg_7 hl 1 ll 0 hh 0 lh0
tle 7209-3r circuit description data sheet 16 rev. 1.0, 2014-02-03 failure encoding in case of multiple faults if multiple faults are stored in the failure regi ster, the faults that are encoded in the diaxx bits can not be displayed simultaneously due to the encoding scheme that is used. in this case, errors are encoded according to the following priority list. ? priority 1: under voltage (p lease note that after removal of under voltage, the original error will be restored, see below) ? priority 2: short circuit across the load ? priority 3: all other short circuits ? priority 4: open load if a failure of higher priority is detected, the failures of lower priority are no longer visible in the encoded spi message. fault storage and reset of the diagnosis register dia_reg register dia_reg is reset upon the following conditions: ? with the rising edge of the csn-signal afte r the spi-instruction rd_dia. this reset only takes place if the correct number of 16 sck pulses has been counted. ? when the voltage on dms exceeds the thres hold for detecting spi-mode (after under voltage condition). under volt age on vs (typ. < 5,0v) sets bit 0.... bit 3 of dia_reg to 0000. if vs rises above the under volt age level, bits of dia_reg are restored (when dms > 3.5v). ? a rising edge on en while dis=0 or a falling edge on dis while en=1 re-activates the output power-stages, and rese ts the dia_reg register. table 10 encoding of the diagnostic bits of out1 and out2 dia21 dia20 dia11 dia10 description latch behavior 1 1 0 0 short circuit over load (scol) latched - - 0 1 short circuit to battery on out1 (scb1) latched - - 1 0 short circuit to ground on out1 (scg1) latched - - 1 1 no error detected on out1 - 0 0 1 1 open load (ol) latched 0 1 - - short circuit to battery on out2 (scb2) latched 1 0 - - short circuit to ground on out2 (scg2) latched 1 1 - - no error detected on out2 - 0 0 0 0 under voltage on pin vs not latched
tle 7209-3r circuit description data sheet 17 rev. 1.0, 2014-02-03 2.4.2.7 data-byte: device identifier and version (spi instructions rd_ ident and rd_version) the ic?s identifier (device id) and version number are used for production test purposes and features plug & play functionality dependi ng on the systems software release. the two numbers are read-only accessible via the spi instructions rd_ident and rd_version as described in section 2.4.2.4 . the device id is defined to allow identification of different ic-types by software and is fixed for the TLE7209-3R. the version number may be utilized to dist inguish different states of hardware and is updated with each redesign of the TLE7209-3R. the contents is divided into an upper 4 bit field reserved to define revisions (swr) corresponding to specific software releases and a lower 4 bit field utilized to identify the actual mask set revision (msr). both (swr and msr) will start with 0000 b and are increased by 1 every time an according modification of the hardware is introduced. reading the ic identifier (spi instruction: rd_ident): reading the ic version number (spi instruction: rd_version): table 11 device identifier format msb 76543210 id7 id6 id5 id4 id3 id2 id1 id0 table 12 device identifier description bit name description 7...0 device-id(7...0) id-no.: 10100010 table 13 ic version number format msb 76543210 swr3 swr2 swr1 swr0 msr3 msr2 msr1 msr0 table 14 ic version number description bit name description 7...4 swr(3...0) this register is set to 0 3...0 msr(3...0) version corresponding to mask set
tle 7209-3r circuit description data sheet 18 rev. 1.0, 2014-02-03 2.4.2.8 open-load diagnosis open-load diagnostic in off-state is only possible in the spi-mode (dms = 5 v) if the device is disabled (en = l or dis = h) . the detection mechanism is depicted in figure 9 . the according diagnostic information can be read out via the spi diagnostic register. the resulting overall diagnostic truth-table is shown as table 15 figure 9 functional block diagram of open-load detection table 15 diagnosis truth table for open load detection output stage inactive, en = low or dis = high, dms > 4.5 v out1 out2 load available h h open load h l ol detected sc -> gnd on out1 and open load l l ol not detected ? double fault sc -> gnd on out2 and open load h l ol detected sc -> v s on out1 and open load h l ol detected sc -> v s on out2 and open load h h ol not detected ? double fault 1.5ma out1 or en dis dms and - + 1v 1ma out2 - + 1v and 1 to diagnostic register v s v s
tle 7209-3r electrical characteristics data sheet 19 rev. 1.0, 2014-02-03 3 electrical characteristics note: maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. 3.1 absolute maximum ratings pos. parameter sym- bol limit values unit test conditions min. max. 3.1.1 junction temperature t j -40 +150 c? ? +175 c dynamic: t < 1 s 3.1.2 storage temperature t s -55 +125 c? 3.1.3 ambient temperature t a -40 +125 c? 3.1.4 supply voltage v s -1 40 v static destruction proof -2 40 v dynamic destruction proof t < 0.5 s (single pulse, t j < 85 c) 3.1.5 voltage at logic inputs in1, in2, dis, en, sdi, sck/sf v -0.5 18 v in status-flag-mode, sf pull-up r 10 k 3.1.6 voltage at logic input csn v -0.5 40 v 3.1.7 voltage at logic input dms v dms -0.5 18 v ? 3.1.8 voltage at logic output sdo v -0.5 v dms +0.5 v? 3.1.9 esd susceptibility hbm according to eia/jesd22-a114-b (1,5kohm, 100pf) v esd ? ? 4kv all pins 3.1.10 v esd-- out ? ? 8kv only pins 6, 7, 14 and 15 (outputs)
tle 7209-3r electrical characteristics data sheet 20 rev. 1.0, 2014-02-03 3.2 operating range pos. parameter sym- bol limit values unit remark min. max. 3.2.1 supply voltage v s 528v 3.2.2 dms supply voltage v dms 3.5 5.5 v device in spi-mode 3.2.3 pwm frequency f ? 30 khz may be limited to lower values in the application due to switching losses or duty cycle requirements 3.2.4 junction temperature t j -40 150 c note: in the operating range, the circuit f unctionality as described in the circuit description is fulfilled. 3.3 thermal resistance 3.3.1 junction-case r thjc ? 1.5 k/w specified by design 3.3.2 junction-ambient r thja ? 50 k/w minimal footprint 3.4 electrical characteristics 5v < v s < 28v; ? 40 c < t j < 150 c; unless otherwise specified pos. parameter symbol limit values unit test conditions min. typ. max. power supply 3.4.1 under voltage at v s v uv off 3.4 4.2 5 v switch off threshold v uv on 3.6 4.4 5.2 switch on threshold v uv hy 100 ? 1000 mv hysteresis 3.4.2 supply current i ub ??30ma f = 20 khz, i out = 0 a ??20ma f = 0 hz, i out = 0 a
tle 7209-3r electrical characteristics data sheet 21 rev. 1.0, 2014-02-03 logic inputs in1, in2, dis, en 3.4.3 input ?high? v ih 2??v? 3.4.4 input ?low? v il ??1v? 3.4.5 input hysteresis v ih y 0.1? 0.6v ? 3.4.6 pull-up current in1, in2, dis i il -200 -125 ? a u 1 v 3.4.7 pull-down current en i ih ? ? 100 a u 2 v power outputs out1, out2 3.4.8 switch on resistance ? ? ? 300 m r out-ub , r out-gnd v s > 5 v, i out = 3 a 3.4.9 switch-off current | i l | 5.56.67.7a -40 c < t j < t ilr 1.42.53.6a t j = t sd ; specified by design 3.4.10 switch-off time t a 81626 s vs=13.2 v, l=2.2 mh, r=0.23 3.4.11 blanking time t b 81319 s vs=13.2 v, l=2.2 mh, r=0.23 3.4.12 switch-off tracking t a / t b 1.0 ? ? ? vs=13.2 v, l=2.2 mh, r=0.23 3.4.13 short circuit detection current | i ouk | 8?18a? 3.4.14 current tracking | i ouk | - | i l | 2 3.5 ? a specified by design 3.4.15 reactivation time after internal shut-down t ? ? 200 s over-current- or over- temperature shut- down to reactivation of the output stage note: reactivation time is not subject to production test; s pecified by design 3.4 electrical characteristics (cont?d) 5v < v s < 28v; ? 40 c < t j < 150 c; unless otherwise specified pos. parameter symbol limit values unit test conditions min. typ. max.
tle 7209-3r electrical characteristics data sheet 22 rev. 1.0, 2014-02-03 3.4.16 leakage current ? ? ? 200 a output stage switched off 3.4.17 free-wheel diode forward voltage u d ??2v i out = 3 a 3.4.18 free-wheel diode reverse recovery time t rr ? ? 100 ns reverse recovery time is not subject to production test; specified by design output status-flag, open drain output dms < 0.8 v 3.4.19 output ?high? (sf not set) i sf ??20 a v sf = 5 v 3.4.20 output ?low? (sf set) i sf 300 ? ? a v sf = 1 v 100 ? ? a v sf = 0.5 v timing 3.4.21 output on-delay t don ??6 s in1 --> out1 resp. in2 --> out2, i out = 3 a 3.4.22 output off-delay t doff ??6 s in1 --> out1 resp. in2 --> out2, i out = 3 a 3.4.23 output switching time t r , t f ??5 s out1h --> out1l, out2h --> out2l, i out = 3 a out1l --> out1h, out2l --> out2h 3.4.24 disable delay time t ddis ??2 s dis --> outn, en --> outn 3.4.25 power on delay time ? ? ? 1 ms v s = on --> output stage active; no load 3.4.26 delay time for fault detection t df 1.0 2 ? s specified by design 3.4.27 minimum pulse width t den ?1.62.2 s en/dis-->reset dia_reg 3.4 electrical characteristics (cont?d) 5v < v s < 28v; ? 40 c < t j < 150 c; unless otherwise specified pos. parameter symbol limit values unit test conditions min. typ. max.
tle 7209-3r electrical characteristics data sheet 23 rev. 1.0, 2014-02-03 input sck, spi clock input 3.4.28 low level u sckl ??1v? 3.4.29 high level u sckh 2??v? 3.4.30 hysteresis u sck 0.1? 0.4v ? 3.4.31 input capacity c sck ??20pf? 3.4.32 input current - i sck ?2050 a pull-up current source connected to v cc input csn, chip select signal 3.4.33 low level u csnl ? ? 1 v TLE7209-3R is selected 3.4.34 high level u csnh 2??v? 3.4.35 hysteresis u csn 0.1? 0.4v ? 3.4.36 input capacity c csn ??20pf? 3.4.37 input current - i csn ?2050 a pull up current source connected to v cc input sdi, spi data input 3.4.38 low level u sdil ??1v? 3.4.39 high level u sdih 2??v? 3.4.40 hysteresis u sdi 0.1? 0.4v ? 3.4.41 input capacity c sdi ??20pf? 3.4.42 input current - i sdi ?2050 a pull up current source connected to v cc 3.4 electrical characteristics (cont?d) 5v < v s < 28v; ? 40 c < t j < 150 c; unless otherwise specified pos. parameter symbol limit values unit test conditions min. typ. max.
tle 7209-3r electrical characteristics data sheet 24 rev. 1.0, 2014-02-03 output sdo tristate output of the TLE7209-3R (spi output); 3.4.43 low level v sdol ??0.4v i sdo = 2 ma 3.4.44 high level v sdoh v dms - 0.75 ??v i sdo = -2 ma 3.4.45 capacity c sdo ? ? 30 pf capacity of the pin in tristate 3.4.46 leakage current i sdo -10 ? 10 a in tristate note: all in- and output pin capacities are not subject to production tes t; specified by design input dms supply-input for the spi-interface and selection pin for spi- or sf-mode 3.4.47 input voltage v dms 3.5 ? ? v spi-mode v dms ? ? 0.8 v status-flag-mode 3.4.48 input current i dms ??10maspi-mode open-load diagnosis 3.4.49 diagnostic threshold v out1 0.8? 2.0v dms>4.5v, en < 0.8 v or dis > 4.5 v; no load v out2 0.8? 2.0v 3.4.50 pull-up current - i out1 1000 1500 2000 a v out1 =0 v, dms > 4.5 v, en < 0.8 v or dis > 4.5 v; no load 3.4.51 pull-down current i out2 700 1000 1400 a v out2 =5 v, dms > 4.5 v, en < 0.8 v or dis > 4.5 v; no load 3.4.52 tracking diag. c ? 1.2 1.5 1.7 ? i out1 / i out2 3.4.53 delay time t d 30 ? 100 ms ? note: open load is detected if v out1 > 2 v and v out2 < 0.8 v (refer to fig. 9). 3.4 electrical characteristics (cont?d) 5v < v s < 28v; ? 40 c < t j < 150 c; unless otherwise specified pos. parameter symbol limit values unit test conditions min. typ. max.
tle 7209-3r electrical characteristics data sheet 25 rev. 1.0, 2014-02-03 spi timing (see figure 13) 3.4.54 cycle-time (1) t cyc (1) 200 ? ? ns referred to master 3.4.55 enable lead time t lead (2) 100 ? ? ns referred to master 3.4.56 enable lag time t lag (3) 150 ? ? ns referred to master 3.4.57 data valid t v (4) ? ? ? ? 40 150 ns ns c l = 40 pf c l = 200 pf referred to tle7209- 3r 3.4.58 data setup time t su (5) 50 ? ? ns referred to master 3.4.59 data hold time t h (6) 20 ? ? ns referred to master 3.4.60 disable time t dis (7) ? ? 100 ns referred to tle7209- 3r; specified by design 3.4.61 transfer delay t dt (8) 150 ? ? ns referred to master 3.4.62 select time t csn (9) 50 ? ? ns referred to master 3.4.63 access time t acc (10) 8.35 ? ? s referred to master 3.4.64 clock inactive before chip select becomes valid (11) 200 ? ? ns ? 3.4.65 clock inactive after chip select becomes invalid (12) 200 ? ? ns ? temperature thresholds 3.4.66 start of current limit reduction t ilr 150 165 ? c 3.4.67 thermal shut-down t sd 175 ? ? c note: temperature thresholds are not subjec t to production test; specified by design 3.4 electrical characteristics (cont?d) 5v < v s < 28v; ? 40 c < t j < 150 c; unless otherwise specified pos. parameter symbol limit values unit test conditions min. typ. max.
tle 7209-3r timing diagrams data sheet 26 rev. 1.0, 2014-02-03 4 timing diagrams figure 10 output delay time--depicted for low-side fets figure 11 disable delay time 80% 20% t don 50% 50% t doff outx inx 0 5 v z 20% t ddis 50% outx dis / en 0 5 v
tle 7209-3r timing diagrams data sheet 27 rev. 1.0, 2014-02-03 figure 12 output switching time figure 13 spi-timing 80% 20% t rise t fall outx 20% 80% sdo sdi msb in bit (n-4)...1 lsb in bit (n-4)...1 1 4 5 6 sck csn 7 8 n = 16 9 10 3 2 bit (n-3) bit 0; lsb tristate bit (n-3) bit (n-2) 11 12
tle 7209-3r application data sheet 28 rev. 1.0, 2014-02-03 5 application figure 14 application example with spi-interface figure 15 application example with status-flag dms in2 sdo sck/sf sdi csn en v s gnd out 2 out 1 dis m in1 c from watchdog or fail-safe controller vcc v-reg 100f vs < 40v 100nf 100nf dms in2 sdo sck/sf sdi csn en v s gnd out 2 out 1 dis m in1 c from watchdog or fail-safe controller v-reg vcc 47k 100f vs < 40v 100nf
tle 7209-3r application data sheet 29 rev. 1.0, 2014-02-03 figure 16 application examples for over-voltage- and reverse-voltage protection 100nf 100f main relay ignition switch tle 7209-3r v s battery vs < 40v reverse polarity protection via main relay
tle 7209-3r package outlines data sheet 30 rev. 1.0, 2014-02-03 6 package outlines green product (rohs compliant) to meet the world-wide customer requireme nts for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). heatslug 1 10 110 index marking does not include plastic or metal protrusion of 0.15 max. per side 1 x 45? (mold) 15.9 1) ?.15 a -0.2 (metal) 13.7 0 +0.1 +0.13 0.4 20 11 0.25 m a 1.27 1.2 -0.3 (heatslug) 15.74 ?.1 (metal) 0.25 heatslug (mold) 20x 11 3.2 14.2 ?.3 20 ?.1 0.95 3.25 3.5 max. 0.1 1.3 ?.1 -0.02 +0.07 6.3 0.25 ?.15 2.8 11 1) b (metal) 5.9 b ?.1 ?.15 5? ?? 1) pg-dso-20-65 (plastic dual small outline package) gps05791 dimensions in mm for further information on alternativ e packages, please vi sit our website: http://www.infineon.com/packages .
tle 7209-3r package outlines data sheet 31 rev. 1.0, 2014-02-03 7 revision history rev. date changes 0.1 2012-09-18 initial target data sheet 1.0 2014-02-03 data sheet page 19, pos. 3.1.9, 3.1.10 : esd hbm standard changed to eia/jesd22-a114-b
edition 2014-02-03 published by infineon technologies ag 81726 munich, germany ? 2014 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the applic ation of the device, in fineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery term s and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may c ontain dangerous substances. for information on the types in question, pleas e contact the nearest infi neon technologies office. infineon technologies components may be used in li fe-support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-suppor t device or system or to affect the safety or effectiveness of that device or s ystem. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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